Device screening test and operation margin test of conventional semiconductor integrated circuits are performed by an LSI tester. With the increasing scale of LSI and increasing complexity of functions, there is often a case wherein it is not possible to detect a fault or fail only by testing a critical path of logic delay. An LSI that has passed the test causes an operational fault on an actual product on which the LSI is mounted.
Consequently, in order to prevent a failure in detection of a fault or fail, a technique is used in which the LSI is mounted on a printed circuit board of an actual device, or a test printed circuit board simulating an actual device, and an overall system is operated to perform a test.
In a test of an LSI, in general, the test is performed under more severe conditions that actual operational conditions, and an LSI having an operation margin to some extent is selected and shipped. However, as described above, when a test of an LSI is performed under the condition that the LSI is mounted on the printed circuit board, it is not possible to test the margin while adjusting operational frequency of the LSI. For example, in general, in case an operational test is performed with the overall system, it is necessary to operate an interface of a LAN (Local Area Network), a USB (Universal Serial Bus), a HDD (Hard Disk Drive), a video signal or the like.
With respect to this type of interface, since the operational frequency, allowable duty ratio, and the like, are not prescribed by a specification, it is not possible to change the frequency of a system reference clock, in order to perform an operation by the overall system.
A reference clock supplied from outside an LSI to the LSI is generally supplied from a crystal oscillator. The oscillation frequency of this crystal oscillator is determined at the time of manufacture, and it is not possible to perform adjustment thereafter.
Since a clock signal inside an LSI, in general, is generated by a Phase Locked Loop (referred to as PLL), it is not possible to adjust duty ratio or the like of the clock signal inside the LSI from outside the LSI.
Thus, with regard to an LSI mounted on a printed circuit board, it is not possible to adjust a clock signal from the outside.
Consequently, in order to perform the operation margin test on the semiconductor integrated circuit, it is necessary to mount a circuit for adjusting period, duty ratio, delay, and the like, of the clock signal inside the LSI.
With a conventional LSI tester, when performing a test of the semiconductor integrated circuit, it is possible to adjust operational frequency inside the semiconductor integrated circuit by adjusting the clock frequency which the LSI tester applies to the semiconductor integrated circuit. In this way, it is possible to test the operation margin of the semiconductor integrated circuit.
However, in general, the semiconductor integrated circuit has the Phase Locked Loop (PLL) internally, and a clock signal inside the semiconductor integrated circuit uses a clock output by this PLL. As a result, adjusting duty ratio, phase offset, or the like, of a clock inside the semiconductor integrated circuit from outside is not possible as long as a dedicated circuit for adjusting these is not provided.
From these types of problems, there has been proposed a technique of mounting a circuit for adjusting the period of the clock signal inside the semiconductor integrated circuit, and performing the operation margin test (Patent Document 1: U.S. Pat. No. 6,127,858, and Patent Document 2 (U.S. Pat. No. 6,891,421 (B2)).
With this circuit being mounted, it is possible to adjust a clock period and a duty ratio inside a semiconductor integrated circuit mounted in an actual device.
Conventional examples of a circuit that can control delay of a clock signal in a semiconductor integrated circuit, by a clock adjusting circuit mounted in the semiconductor integrated circuit, include Patent Document 3 (U.S. Pat. No. 5,945,862) and Patent Document 4 (U.S. Pat. No. 6,125,157).
These circuits are able to shift, without limitation, a clock phase. Using this characteristic, a DLL (Delay Locked Loop) function that makes either a rising edge or a falling edge of an output clock coincide with timing of a reference clock edge, is realized.
In performing a test of timing margin or the like, by a semiconductor integrated circuit mounted on a printed circuit board, it is necessary to mount a circuit for adjusting the period, the duty ratio, or the like, of a clock signal, on the semiconductor integrated circuit.
In Patent Document 1 (U.S. Pat. No. 6,127,858), and Patent Document 2 (U.S. Pat. No. 6,891,421(B2)) that disclose a circuit for adjusting the period or the like of the clock signal, inside a semiconductor integrated circuit, as described above, a circuit as shown in FIG. 1 is proposed. This circuit can adjust the clock period, the clock duty ratio, or the like, by dynamically switching delays of clock signals. In an example of FIG. 1, a coarse delay adjustment is performed by delay elements and a selector, and a detailed delay adjustment is performed by a variable delay circuit. The variable delay circuit is realized by a switch which changes over driving capability of a transistor. For example, when the selector is switched so that the delay is shortened, since a next clock phase is made fast with respect to a previous clock, the clock period becomes shorter, only for one clock cycle in which switching of delay is performed. Conversely, when switching is performed so that the delay is increased, a next clock phase is delayed, and the clock period of this instant is elongated. Though this system can with ease perform expansion and shortening of the clock period, the number of clock cycles in which the clock period can be expanded and shortened is limited by the number of stages of delay element. Since the delay amount of one delay element stage fluctuates due to variations, a user cannot accurately know how much the clock period fluctuates, by one-stage switching of the delay.
Meanwhile, in order to detect a fault and fail of the semiconductor integrated circuit, a clock adjusting circuit 23 is preferably built-in inside a semiconductor integrated circuit, as shown in FIG. 2, and with respect to a clock signal of an arbitrary number of cycles,
jitter,
duty ratio,
skew, delay or the like, and
period (frequency)
can be adjusted.
In order to adjust the period (frequency), the duty ratio, the jitter, the delay and the like, of a clock signal (clock pulse) of an arbitrary number of cycles, a function is necessary by which the phase of the clock signal can be shifted without limitation.
In order to realize this, for example, a circuit may be configured in which an arbitrary phase, in which one clock period is divided by N, can be output. In FIG. 2, output of the clock adjusting circuit 23 is supplied as a clock of a logic circuit, an I/O circuit, a memory circuit or the like, via a clock distribution circuit (clock tree buffer) 24. The output clock of the clock distribution circuit 24 is selected via the selector 22, and is received by the PLL 21.
As shown in FIG. 3A, a system is considered, in which a clock edge can be generated at arbitrary timing, wherein one period of a clock is divided by N. If the clock phase is gradually delayed, in due course it is delayed by one period from the original phase. Since a state of a delay of one period is equal to that of the original phase, in order to further delay the phase, a similar operation may be repeated.
Considering this point in FIG. 3B, delaying of the clock phase is a phase rotation on a circle, and this in due course performs one rotation and returns to the original phase.
If it is desired to further delay the phase, the same operation may be performed. Similarly, in case in which the phase is made quick conversely, the circle rotates in a reverse circuit and in due course the clock phase performs one rotation.
In this way, if a circuit is provided in which a clock period (360 degree) is divided approximately equally by N, and a clock of arbitrary phase is extracted from among these N phases, it is possible to delay or to speed up the phase without limitation.
FIGS. 4A and 4B are diagrams showing one example of a configuration of a phase shifter in which one clock period is divided by N, and an arbitrary phase clock thereof is produced.
In an L phase clock generation circuit 44, an L phase clock (L is an integer) is generated. The L phase clock generation circuit 44 has L output terminals, and clock phases output from the L output terminals are each shifted by 360/L degrees. A phase shifter 40 includes selectors 41 and 42 which receive L phase clock signals from the L output terminals from the L phase clock generation circuit 44, and a phase compensation circuit 43. Phase control signals are supplied to the selectors 41 and 42 and the phase compensation circuit 43.
The selectors 41 and 42 select two clock signals from the L clock signals. In the selectors 41 and 42, a phase of a clock signal output from clock output is coarsely determined. The two signals selected by the selectors 41 and 42 have neighboring phases, a phase difference of which is 360/L degrees.
The two clock signals selected by the selectors 41 and 42 are received by the phase compensation circuit 43. The phase compensation circuit 43 receives two clock signals whose phase is shifted, compensates the phases of the two clock signals in M stages, and outputs an intermediate phase.
If the phases of the two received clock signals are of x degrees and y degrees, with respect to an output clock, it is possible to output an arbitrary phase between x and y, at intervals of every (x−y)/M degrees. In this way, by dividing more finely the clock phase selected by the selector, the phase of the clock output is adjusted.
For example, in case of L=8, and M=16, clock signals at intervals of every 45 degrees are produced by the L phase clock generation circuit, and the phase compensation circuit can adjust the phase of the clock signal at intervals of every 45/16=2.8125 degrees, and can output a clock signal of any one in phases obtained by dividing one period clock signal into (L×M=) 128 stages.
Under this condition, in generating a clock of 25 degrees, for example, clocks of 45 degrees and 90 degrees are selected by a selector circuit.
The phase compensation circuit 43 can produce a clock with a phase difference of 4-stage (2.8125×4=11.25) from 45 degrees by compensating the 45 degree clock and the 90 degree clock at a ratio of 12:4.
FIG. 5 is a diagram showing another configuration example of a phase shifter. In this example, all L phase clock signals from an L phase clock generation circuit 53 are phase-shifted using L phase compensation circuits 51, and L phase clock signals are generated and then, an arbitrary phase is generated by selecting one among these, by a selector 52.
Similar to a case of FIG. 4B, a case is considered in which the L phase clock generation circuit outputs an 8-phase clock, and the phase compensation circuit compensates the phase in 16 stages (M=16).
Here, in generating a 56.25 degree clock, each phase compensation circuit compensates two received clock signals at a ratio of 12:4.
As a result, 11.25 degrees, 56.25 degrees, 101.25 degrees, 146.25 degrees, 191.25 degrees, 236.25 degrees, 281.25 degrees, and 326.25 degrees are output from the respective phase compensation circuits 51, of which there are 8. If 56.25 degrees, which is the second phase, is selected from among these by the selector and output, it is possible to output a desired phase clock.
FIG. 6 is an example in which a multi-phase clock generation circuit used in the phase shifters 40 and 50 of FIGS. 4A, 4B and FIG. 5 is configured by the phase locked loop (PLL). The phase locked loop (PLL) includes a phase comparator 61 which compares a reference clock and a phase of an output clock of an oscillator 64, a charge pump 62 which generates a voltage corresponding to a comparison result of the phase comparator 61, and a loop filter 63 which smoothes an output of the charge pump 62; the oscillator (VCO) 64, which receives an output voltage of the loop filter 63 as a control voltage, outputs a clock of an oscillation frequency corresponding to the control voltage. The oscillator (VCO) 64 includes a first stage inverter 65 and multi-stage delay circuits (non-inverting buffer) 66 (inverter 2-stage configuration) which compose a ring oscillator in which output of a final stage is fed-back as input to the first stage. By using a circuit that can generate equally spaced delays, and extracting clock signals with equally spaced delays, in the oscillator 64, a multi-phase clock can be obtained.
FIG. 7 is an example in which a multi-phase clock generation circuit is configured by a delay locked loop (DLL). The phase locked loop (PLL) includes a phase comparator 71 which compares phases of a reference clock and an output clock of a delay circuit sequence, a charge pump 72 which generates a voltage corresponding to a comparison result of the phase comparator 71, and a loop filter 73 which smoothes output of the charge pump 72; the delay circuit sequence, which receives an output voltage of the loop filter 73 as a control voltage, makes delay time variable. By using a circuit 74 that can generate equally spaced delays, and extracting clock signals with equally spaced delays, in the delay circuit sequence in the delay locked loop, a multi-phase clock can be obtained.
FIG. 8A is an example in which the multi-phase clock generation circuit is configured by a clock divider. A D-type flip-flop 811 receives at a data input terminal D thereof a signal obtained by inverting an output of a D-type flip-flop 814 by an inverter 83, and outputs an output signal of a data output terminal Q and an inverted signal thereof, as Q0, and /Q0. By configuring a state machine circuit of a type in which an internal state goes around once in an arbitrary cycle, it is possible to obtain a multi-phase clock signal. FIG. 8B shows a timing chart of an operation example thereof. In case an L-phase clock is generated by this circuit, in general, the frequency of an output clock is 1/L of the frequency of an input clock.
FIG. 9A is an example in which the multi-phase clock generation circuit is configured of delay elements and phase compensation circuits (PI). The phase compensation circuits 93 and 94 are circuits which output a signal with a phase that is intermediate between two input signals. The phase compensation circuit (PI) 93 receives an input clock A and a signal B delayed by a three-stage delay circuit (non-inverting buffer) 91, and outputs a signal with a phase intermediate therebetween, differentially. The phase compensation circuit (PI) 94 receives a signal B delayed by the three-stage delay circuit (non-inverting buffer) 91 and a signal /A obtained by inverting the input clock A by an inverter 92, and outputs a signal with a phase intermediate therebetween, differentially. FIG. 9B shows a timing chart of operation of this circuit. A phase that is intermediate between the input clock A and a clock B, which is the input clock A delayed, is C.
If phase difference between A and B is x, the phase of a clock signal output from C has a delay of x/2 compared with the phase of A.
With respect to a clock signal output from D, a phase intermediate between an inverted signal of A (a signal with a delay of 180 degrees from A) and B is output. That is, the phase is x/2+90 degrees delayed, with respect to the phase of clock A. As a result, it is possible to obtain two clocks C and D that have a phase difference of 90 degrees. Combining these inverted signals together, a 4-phase clock every 90 degrees is obtained.
FIGS. 10A and 10B are diagrams showing a configuration example of a phase compensation circuit used in the phase shifters of FIGS. 4A, 4B and FIG. 5. Referring to FIGS. 10A and 10B, there are provided NMOS transistors 101 and 102 having sources coupled together, gates supplied with the inverted signal /A of a clock signal A, and the clock signal A, and drains connected to differential terminals Q and /Q and connected to a power supply via a resistor, respectively; and NMOS transistors 103 and 104 having sources coupled together, gates supplied with the clock B and an inverted signal /B thereof, and drains connected to the drains of the NMOS transistors 101 and 102, connected to the differential terminals Q and /Q, respectively, and connected to a power supply via a resistor. The coupled sources of the NMOS transistors 101 and 102 are connected to a plurality of constant current sources 106 via a plurality of switch transistors 105 that are ON-OFF controlled by control signals C1; and the coupled sources of the NMOS transistors 103 and 104 are connected to a plurality of constant current sources 108 via a plurality of switch transistors 107 that are ON-OFF controlled by control signals C2. The number of switch transistors 106 and 107 that are turned ON is determined by the control signals C1 and C2, a current value that drives the differential pair 101 and 102 and the differential pair 103 and 104 is controlled, and a compensation ratio (internal division ratio) of the signals A and B is determined. That is, this circuit can compensate and output two phases of the two clock inputs (A and B). Internally, the circuit is configured such that two signals are added (current summing), and voltage is output via a load resistor. A switch elements and control terminals (C1 and C2) that control the switch elements are provided, in order that weightings of the two signals can be changed in current summing. If currents I1 and I2 that flow in the two differential pairs are adjusted by C1 and C2, a balance between a current flowing in the differential pair that receives signal A and a current flowing in the differential pair B can be adjusted. The weightings in the adding two signals is changed by this balance so that it become possible to output a phase close to A, or conversely, to output a phase close to B.
FIG. 11 is a diagram showing an operation principle of the phase compensation circuit. The clock signal A (=cos(ωt)) and the clock signal B (=cos(ωt−φ)), being two clock signals whose phases are shifted, are received and these are added together. Assuming that the two signals are cosine waves, when two signals being added with the same weighting, an addition result Q (=cos(ωt)+cos(ωt−φ)) outputs a phase (=ωt−φ/2) that is intermediate between A and B.
FIGS. 12A to 12C are diagrams showing another configuration example of the phase compensation circuit. As shown in FIG. 12A, as a buffer circuit connected to two clock inputs A and B, a 3-state type is used or a transmission gate is disposed at output, and a plurality of buffers (tri-state buffers) 120 in which output can be set at a high impedance, are provided. A buffer in FIG. 12B has a configuration in which there are provided transmission gates (CMOS transfer gates) 123 and 124 at output of CMOS inverters (121 and 122); a buffer in FIG. 12C has a configuration in which there are provided a PMOS transistor 125 between a power supply and a source of a PMOS transistor 126 forming a CMOS inverter, and an NMOS transistor 128 between ground and a source of an NMOS transistor 127 forming a CMOS inverter, and complementary control signals /C and C are received by gates of the PMOS transistor 125 and the NMOS transistor 128. By controlling, among these plural buffers 120, the number of those that have outputs kept at a high impedance, and those that operate as a normal buffer, by the control signals C1 and C2, proportions in which the two clock signals are mixed, are adjusted. In this way, the two clock phases given by A and B are compensated and output from Q.
FIG. 13 is a diagram (refer to Patent Document 3) showing one example of a configuration of a delay adjustment circuit that uses a phase shifter. Referring to FIG. 13, the delay adjustment circuit 130 includes the phase shifter 131, a counter 132, and a phase comparator 133.
The counter 132 receives output of the phase comparator 133, counts an input clock, and outputs a count value as a control signal to the phase shifter 131. Phases of a reference clock and an output clock are compared by the phase comparator 133, and responsive to a comparison result thereof, the phase of the output clock is advanced or delayed, and a delay between the input clock and the output clock is adjusted to a desired value. The delay adjustment circuit that uses this type of configuration is referred to in Patent Documents 3 and 4 (U.S. Pat. No. 5,945,862, U.S. Pat. No. 6,125,157).
FIG. 14 shows an example of a timing chart in case a circuit of FIG. 13 is used to operate a phase shifter. FIG. 14 shows respective timing waveforms of an input clock, a control signal, and an output clock. If a phase shift is performed by this circuit, a phase of a clock signal becomes unstable at an instant at which a value of the control signal changes and the phase shifter switches a clock phase. This results in generating jitter that is not intended by a user. In case the control signal is operated with a period the same as a clock period, since only a phase of an edge on one side of the clock signal can be shifted, it is not possible to adjust duty.
In the circuit configuration of FIG. 13, in general, since the control signal of the phase shifter 131 can only adjust a clock phase output by the phase shifter 131 one stage at a time, it is not possible to rapidly expand or shorten the clock period.
In order to expand or shorten the clock period over a plurality of cycles, it is necessary to also increase or reduce the period of the reference clock. That is, the circuit with the configuration of FIG. 13 does not have a function for expanding or shortening the clock period autonomously.
[Patent Document 1]
    U.S. Pat. No. 6,127,858[Patent Document 2]    U.S. Pat. No. 6,891,421(B2)[Patent Document 3]    U.S. Pat. No. 5,945,862[Patent Document 4]    U.S. Pat. No. 6,125,157